As one example of a conventional complementary MIS (CMIS) circuit, a buffer circuit 1 is shown in FIG. 1. The buffer circuit 1 shown uses MOS transistors as MIS transistors. The buffer circuit 1 includes a P-channel MOS (hereinafter referred to as PMOS) transistor 11 having its source electrode S.sub.1 connected to a power supply terminal 2, and an N-channel MOS (hereinafter referred to as NMOS) transistor 12 having its source electrode S.sub.2 grounded. The MOS transistors 11 and 12 have their respective gate electrodes G.sub.1 and G.sub.2 connected in common to an input terminal 3, and have their respective drain electrodes D.sub.1 and D.sub.2 connected in common to an output terminal 4.
A conventional CMOS circuit such as one described above has a problem that when the circuit changes from one stable state to the other stable state, a large shoot-through current flows. Let it be assumed that an input voltage V.sub.IN which slopes slightly when it rises and falls as shown in FIG. 2 is applied to the input terminal 3 as an input signal. When the input voltage V.sub.IN rises from a low level to a high level, both of the PMOS and NMOS transistors 11 and 12 become concurrently conductive during an interval A between a point a.sub.1 when the input voltage reaches the threshold voltage V.sub.TN of the NMOS transistor 12 and a point a.sub.2 when the input voltage reaches the threshold voltage V.sub.TP of the PMOS transistor 11, which causes a large current ("shoot-through current") to flow through the two MOS transistors of the circuit.
Similarly, when the input voltage V.sub.IN falls from the high level to the low level, a shoot-through current will flow during an interval B between a point b.sub.1 when the input voltage V.sub.IN reaches the threshold voltage V.sub.TP of the PMOS transistor 11 and a point b.sub.2 when the input voltage reaches the threshold voltage V.sub.TN of the NMOS transistor 12.
Such a shoot-through current increases the power consumption in the circuit. Increase of power consumption is particularly significant in a circuit in which large-sized transistor are used as the transistors 11 and 12 in order to increase driving capability, because a very large shoot-through current will flow when the circuit state is inverted.
Accordingly, it is an object of the present invention to provide a complementary MIS integrated circuit comprising PMIS and NMIS transistors with their drain electrodes connected together, which has a shoot-through current reduced by making zero or as short as possible an interval during which both transistors become concurrently conductive at the time when the circuit changes from one stable state to the other.